Generate an FPGA Control Carrier with AI: Refusal Guide

MakeIRL's generator treats a FPGA control carrier prompt as a module carrier. Current status: refused.

Bare FPGA and complex FPGA-module carriers are refused because high-speed interfaces, bank voltages, configuration, BGA escape, PDN, multilayer routing, and BOM size exceed the envelope.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact FPGA or complete module, package/connector map, banks/voltages, clocks, configuration flash/mode, reset, debug, and firmware image
2. All rails and sequence, current transients, decoupling, thermal loss, high-speed interfaces, stackup, impedance, fan-out, and connectors
3. Mechanical retention, cooling, assembly/X-ray, boundary scan, programming/recovery, test fixture, compliance, and qualified review

Block plan:

• No bare FPGA/BGA or high-speed module block
• Possible future complete-module carrier only after immutable connector/power/thermal evidence
• Only bounded low-speed ports could connect to ordinary verified carrier blocks

Interfaces: unsupported high-speed transceivers/memory, banked GPIO, possible low-speed I²C/UART subset. Power plan: FPGA rails, sequence and transient PDN exceed the single cataloged low-voltage carrier power contract.

• A real carrier needs connector/bank escape, reference planes, high-speed launches, PDN, clock returns, cooling, and mechanical retention co-designed.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Return a refusal and do not invent connector pins, rail sequence, bank voltage, configuration mode, stackup, impedance, or timing.
2. S1Catalog and exact-MPN provenance. Every FPGA control carrier block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review module/FPGA documentation, SI/PI, clocks, bank constraints, thermals, configuration security, assembly, test coverage, and failure recovery.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• An FPGA can configure while an I/O bank is powered incorrectly or a high-speed link lacks margin, making a boot test false reassurance.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Separately engineered hardware needs rail sequence/current, configuration/recovery, boundary scan, all-bank I/O, link margin, thermal, EMC, and long-run tests.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse bare FPGA, BGA fan-out, high-speed interfaces, multiple rails, memory, HDI/multilayer, or large BOM requests.
• Do not classify a complete FPGA module as a simple MCU carrier without checking every exposed power and high-speed interface.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.