Vibecode a High-I/O Controller PCB: AI Refusal Design Guide

MakeIRL's generator treats a high-I/O controller prompt as a self-contained project board. Current status: refused.

Dense BGA/QFP fan-out, high-speed interfaces, multiple bank rails, multilayer stackups, and large BOMs exceed the current two-layer low-speed carrier envelope.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact processor/FPGA/module, package/ball map, I/O banks and voltages, interfaces/edge rates, clocks, memory, boot, and configuration
2. Rail sequence/current/transients, decoupling/PDN, thermal loss, stackup, impedance, fan-out/vias, connector, and EMC
3. Mechanical outline, layer/HDI supplier, assembly class/X-ray, boundary scan, fixtures, firmware, compliance, and release reviewer

Block plan:

• No dense processor/FPGA/BGA block under current envelope
• Potential decomposition into a complete reviewed compute module plus low-speed cataloged carrier blocks
• High-speed, memory, PDN, BGA fan-out, and multilayer routing remain external engineering work

Interfaces: unsupported high-speed buses, multiple I/O banks, possible low-speed carrier subset after decomposition. Power plan: Multiple rails and high simultaneous-switching current are outside the current 2-layer, ≤40-line, ≤12 V/2 A carrier model.

• Engineering must co-design package fan-out, stackup, bank references, PDN, clocks, connectors, thermal path, and assembly/test access.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. The correct generator output is refusal, with no invented ball map, layer stack, via technology, memory topology, rail sequence, or high-speed route.
2. S1Catalog and exact-MPN provenance. Every high-I/O controller block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review primary datasheets, package escape, SI/PI, thermal, EMI, firmware, manufacturing capability, X-ray, boundary scan, and product requirements.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A dense controller can boot while one bank, return path, memory corner, or power transient remains marginal and fails only at rate or temperature.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• A separately engineered design needs rail/clock sequencing, boundary scan, interface margin tests, thermal and EMC work, manufacturing coupons, and full I/O fixtures.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse dense BGA/QFP high-I/O, high-speed, memory, multilayer/HDI, large BOM, or multiple-rail processor requests.
• Recommend architectural decomposition without claiming MakeIRL generated the high-I/O core.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.