Vibecode a Camera Trigger PCB with AI and Gate Checks Guide

MakeIRL's generator treats a camera trigger prompt as a self-contained project board. Current status: in envelope needs block.

A low-voltage trigger interface can fit after an exact camera/cable and isolated/open-collector block is verified. The current catalog has neither and must not guess the remote pinout.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact camera model, remote connector/cable MPN and measured pinout, focus/shutter behavior, voltage, current, polarity, and shared contact
2. Isolation/open-drain topology, leakage, on-resistance, timing, local/remote trigger, status, firmware, and fail-safe state
3. Jack orientation, cable strain, enclosure, button placement, ESD exposure, mounting, and supported camera list

Block plan:

• Cataloged controller/module carrier
• Verified camera trigger isolation/open-collector block for the measured electrical interface
• Verified exact jack/cable, local button, status, and USB power blocks

Interfaces: isolated or open-collector focus/shutter, GPIO input, UART/I²C remote control if supported. Power plan: USB low-voltage logic isolated from or safely referenced to the camera remote; never interact with flash trigger high voltage.

• Put ESD at the cable jack, maintain isolation spacing if used, support the connector mechanically, and keep focus and shutter mapping visible.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify measured cable pin map, focus/shutter outputs and common, optocoupler/transistor polarity, no camera backfeed, ESD return, and default-off state.
2. S1Catalog and exact-MPN provenance. Every camera trigger block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review camera documentation and measurements, isolation/leakage, cable variants, connector mechanics, latency, default behavior, and risk to customer equipment.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• A plausible TRS pinout can short or trigger the wrong camera contact, and optocoupler leakage may look like a half-press on sensitive inputs.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Continuity-test without a camera, emulate contacts with instruments, then use a current-limited approved camera to test focus, shutter, timing, cable cycles, and ESD.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse flash shoes/high voltage, unknown camera pinouts, unsupported isolation parts, or claims of universal camera compatibility.
• One measured camera/cable combination does not validate similarly shaped connectors from another model.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.