WeAct STM32H750 Core Board carrier PCB: layout and gate checks

A dependable carrier for the WeAct STM32H750 Core Board starts by treating it as a specific development board, not as an interchangeable member of the STM32 family. This version is built around STM32H750VBT6, uses 32-bit Arm Cortex-M, and occupies about 65 × 29 mm; revision dependent. Its physical implementation is dual-row core board with USB-C and external memory devices. Those details determine the land pattern, carrier outline, programming access, antenna or connector clearance, and which signals are genuinely available after the module maker has used its own pins.

The H750 core board relies on external QSPI flash and often SDRAM to complement the MCU's small internal flash, making memory population and boot configuration board-defining.

Typical reasons to choose it include display and GUI controllers and high-performance data processing prototypes. The useful comparison is therefore not merely processor speed: it is whether the exact memory, radio, connector, power path, exposed I/O, and mechanical envelope match the product that will be built. The row below is the integration baseline that should agree with the schematic, footprint, BOM, assembly drawing, and firmware target.

The carrier power tree must satisfy 5 V USB/VIN with onboard 3.3 V regulation while every external signal respects typically 3.3 V I/O; only explicitly marked FT pins tolerate 5 V. These are separate checks. A board can accept USB or VIN at one connector while its GPIO remains strictly 3.3 V, and an onboard regulator can be safe at idle yet lose regulation during a radio, display, motor, or memory-current burst. Document which source owns each rail, what happens when USB and carrier power are both present, and where bulk and high-frequency decoupling close the current loop.

Keep high-speed memory buses as implemented on the module, route carrier display or camera interfaces over solid references, and preserve SWD plus boot access.

• Use the exact board schematic and mechanical drawing: Nucleo Morpho, Arduino-style headers, Black Pill, Blue Pill, and WeAct core boards use different geometries. Keep ST-LINK jumpers and SWD access reachable.
• Audit each signal against the MCU datasheet for 5 V tolerance, alternate-function mapping, and analog restrictions. Decide whether ST-LINK USB, VIN, E5V, 5V, or 3V3 owns power and isolate competing sources.

Route from a verified pin table rather than a reseller graphic. In particular, treat SWD, USB, FMC/SDRAM, QSPI flash, SDIO, high-speed timers and extensive edge pinsas design constraints that must survive schematic capture, footprint numbering, layout, production programming, and enclosure assembly. Mark orientation on copper or silkscreen, retain recovery/debug access, and make every antenna, cable, card, switch, or connector operable after the carrier is fully populated—not only while it is open on a bench.

A generic DRC run cannot know that a technically connected pin is the wrong boot strap, that a development-board header was mirrored, or that copper under an antenna will ruin range. The useful release check combines KiCad connectivity and fabrication rules with the product-specific conditions below. Each item should be supported by the selected module datasheet, hardware guide, board schematic, or mechanical drawing—not by a footprint name alone.

1. Check header coordinates, pin numbering, board orientation, mounting holes, debugger overhang, and the exact MCU fitted to the board.
2. Check 3.3 V domains, only-documented 5 V-tolerant pins, BOOT0 state, NRST, SWD access, oscillator population, and USB pull or termination parts where applicable.
3. Check power jumpers and backfeed paths and verify every alternate-function assignment against the exact STM32 package, not merely the MCU family name.
4. For WeAct STM32H750 Core Board, verify external flash/SDRAM part numbers, boot mode, clock source, H750 128 KB internal flash limit, USB, and exact header mapping.

After those checks, refill every copper zone, run ERC and DRC from the same revision used to generate fabrication data, and inspect the actual Gerbers, drill file, BOM, and placement output. Confirm that the module ordering code in the BOM matches the memory and radio assumptions in firmware. A carrier is not release-ready when its prototype happens to boot; it is ready when the exact build configuration can be reproduced and inspected.

These failures recur because family names conceal physical and electrical differences. For this particular integration, watch for the following concrete mistakes:

• Building firmware as if it lives entirely in large internal flash can work on H743 but fail on H750 unless external-memory boot is configured.
• Assuming two boards sold under the same color name carry the same genuine MCU, USB pull-up, crystal values, or header pinout.
• Driving a non-FT analog or oscillator-capable pin from 5 V because some other pins on that STM32 family are tolerant.

Sourcing note. Freeze the WeAct board revision and memory devices; the H750VBT6 marking alone does not describe the module's usable memory system. Record the complete manufacturer code, approved alternates, module or board revision, antenna and cable when applicable, memory population, and the firmware build that was tested. If a substitute changes any of those facts, reopen the footprint, power, pinout, radio, and production-programming review instead of treating it as a purchasing-only change.