Vibecode an E-Ink Dashboard PCB with AI and Gate Checks

MakeIRL's generator treats a e-ink dashboard prompt as a self-contained project board. Current status: in envelope needs block.

A low-speed e-ink carrier can fit the intended envelope once the exact display/FPC and level/power block is cataloged. The current seed catalog has no display block.

MakeIRL V2 extracts a strict CarrierSpec from the prompt, applies a deterministic scope policy, resolves only cataloged blocks, composes deterministic connectivity and exact-MPN BOM data, emits KiCad artifacts, and runs the manufacturing gate. The language model does not invent pins, topology, parts, placement, routing, or substitutions.

1. Exact display/module MPN, FPC pinout and contact side, logic voltage, update waveform/current, busy/reset behavior
2. Controller/module, SPI rate, image storage, button behavior, sleep target, refresh and ghosting requirements
3. Display support, FPC bend/latch access, enclosure window, board thickness, mounting, and service path

Block plan:

• Cataloged controller/module carrier
• Verified exact e-ink display/FPC and any required power/level block
• Cataloged USB power, buttons, status, storage, and programming blocks

Interfaces: slow SPI, GPIO busy/reset/data-command, human-input GPIO. Power plan: USB power inside the envelope, including display update peaks; no generated e-ink high-voltage circuit or lithium supply.

• Lock display and FPC mechanics first, keep components out of the glass support area, route SPI with a clean return, and preserve latch access.
• Freeze the board outline, mounting holes, connector faces, component height zones, test access, and keepouts before evaluating generated placement or routing.

Gate checks:

1. S1Generated connectivity and schematic parity. Verify every FPC contact number/view, supply voltage, busy/reset pulls, display power sequence, connector orientation, and update-current headroom.
2. S1Catalog and exact-MPN provenance. Every e-ink dashboard block, footprint, pin map, required companion, BOM line, and block-status claim must resolve to the pinned catalog version; the prompt cannot create missing hardware.
3. S2PCB DRC, fabrication profile, and release identity. Run KiCad DRC and schematic parity, compare geometry with one quoted fab profile, regenerate Gerbers/drills/BOM/CPL from the approved revision, and inspect both local and supplier previews.

• Review fragile display mechanics, waveform and temperature limits, FPC insertion, sleep leakage, image retention/ghosting, and enclosure pressure.
• A reviewer must check primary datasheets, exact symbol-to-footprint mapping, power and protection, return paths, connector orientation, mechanical fit, test coverage, and every gate waiver before release.

Failure modes:

• An FPC can mate while its contact side is reversed, and an e-ink panel may be permanently damaged by the wrong voltage or update sequence.
• ERC and DRC can prove encoded consistency but cannot prove requirements, component source truth, analogue stability, RF/EMI, thermal margin, firmware, safety, compliance, or delivered product function.

Validation plan:

• Refresh full black/white, checkerboard, partial regions, and temperature corners; measure update/sleep current, busy timing, ghosting, and FPC cycles.
• Bring up first articles with current limiting, measure every rail before fitting expensive modules, program minimal test firmware, exercise every interface and fault assumption, and retain measurements against the released revision.

• Refuse invented display boost rails, waveform tables, unknown FPC pinouts, batteries, or unsupported fast display buses.
• A supported carrier does not prove display lifetime, optical quality, or firmware waveform correctness.

The intended carrier envelope is 2-layer FR-4, at most 100 × 100 mm, at most 40 BOM lines, at most 12 V SELV and 2 A, with cataloged modules and low-speed I²C, UART, GPIO, slow SPI, or power-only USB-C connections. The current catalog is narrower than that intended envelope.

Deterministic policy refuses unsupported or hazardous requests, including mains, motors, lithium charging, RF design, switch-mode power, high-speed buses, excessive size/current, and unknown modules. A refusal is a safety and truthfulness result, not a failed attempt to improvise a circuit.

The current seed catalog contains ESP32-C3 carrier, USB-C power, and Qwiic/status-LED blocks at checked status. They have passed deterministic checks but are not yet physically verified through the documented two-lot bring-up ladder; pages must not call those current seeds verified.

The output is a gated design candidate for engineering review. Current placement/routing can still produce blocking or review findings, so a generated board is not automatically fab-ready, functionally validated, certified, or safe to order. MakeIRL does not autonomously place a fabrication order from a prompt. Human review, source and output inspection, gate resolution, order-specific fab confirmation, and physical bring-up remain required.