GCT USB4110-GF-A PCB footprint, checks, and sourcing guide

The GCT USB4110-GF-A is a USB 2.0 Type-C receptacle from GCT. Its package or board interface is compact mid-mount 16-contact SMT receptacle with shell stakes, and its relevant electrical envelope is USB 2.0 and 5 V sink/source designs per Type-C role. It communicates or connects through USB 2.0 and CC. Those fields belong together: substituting a familiar family name while changing package, voltage, sensing port, mount style, current class, or interface behavior can leave a PCB that passes ordinary net checks and still cannot be assembled or function safely.

USB4110 uses a compact, partially recessed body and GCT-specific retention geometry, useful where connector height matters.

Common uses include compact wearables and board-edge USB-C controls. Start with the manufacturer drawing and recommended application, then record the exact ordering suffix alongside the KiCad symbol and footprint. This makes the library evidence reviewable when the part is re-sourced months later.

• Build the footprint from the manufacturer's recommended land pattern, including shell stakes, paste reductions, courtyard, connector-edge datum, and any plated slots. Similar-looking USB-C receptacles routinely use incompatible shield and signal-pad geometry.
• Put the mating face on the PCB edge with enough enclosure and cable-shell clearance. Confirm whether the part is top-mount, mid-mount, or straddle-mount before setting the board outline and finished thickness.

Model the full cable shell and enclosure lip, then route the pair and VBUS out of the dense rear pad field without necking copper below current or fab limits.

• For a USB device or power sink, place one 5.1 kΩ Rd from CC1 to ground and another from CC2 to ground. Do not short CC pins together. Add low-capacitance ESD protection near the receptacle and give its ground a short path to the shell/ground return.
• Join duplicated USB 2.0 A/B contacts according to the connector datasheet, route D+ and D− as a short coupled pair over continuous reference copper, and make VBUS width, fuse, TVS, and power-path components match the current the product actually requests.

Put the support components where their current, thermal, optical, RF, or measurement loops are actually short—not merely where ratsnest lines look tidy. Confirm pin one from the package view used in the datasheet, distinguish top view from mating face or bottom view, and check mask, paste, drill, courtyard, enclosure, and rework access independently. A correct copper pad pattern can still be a bad production footprint when the sensing opening, connector latch, exposed pad, thermal path, or cable volume is wrong.

MakeIRL’s release gate should not stop at “the symbol has the right number of pins.” For this part, a useful gate review combines ERC/DRC with the following package- and function-specific evidence:

1. Compare every signal, CC, VBUS, ground, shield, slot, and mechanical pad against the exact receptacle drawing and check mirrored top/bottom orientation.
2. Check two independent CC resistors, USB D+/D− polarity and continuity, VBUS isolation, ESD placement, and the shell's intentional chassis or circuit-ground connection.
3. Check connector-to-edge alignment, plated-slot capability, annular rings, solder-mask webs, courtyard, cable insertion volume, and enclosure wall thickness.
4. For GCT USB4110-GF-A, verify recessed board-edge geometry, every retention feature, 16-contact pad map, shell grounding, CC1/CC2, and VBUS copper.

Then run ERC and DRC, refill zones, and inspect the fabrication and assembly outputs. Cross-probe the exact pads named by any finding, compare the BOM MPN with the footprint and electrical limits above, and verify that a real cable, enclosure, antenna, sensor stimulus, load, or thermal path can be tested on the assembled unit. An exclusion is evidence that someone dismissed a marker; it is not evidence that the underlying condition was resolved.

The most expensive errors are usually plausible: a footprint from a sibling package, a breakout-board voltage copied to the bare IC, a headline current used without thermal analysis, or a connector family selected by pitch alone. For GCT USB4110-GF-A, review these failure modes explicitly:

• Copying USB4105 pads because both are GCT 16-pin parts can put shell holes and the mating face in the wrong locations.
• Using a footprint named simply USB_C_Receptacle that fits a different vendor's tabs or swaps the two dense pad rows.
• Adding only one CC resistor, which makes a reversible plug work in one orientation and fail in the other.

Sourcing note. Use the exact USB4110-GF-A drawing and packaging suffix; qualify connector insertion life for the product. The approved vendor list should preserve manufacturer, full suffix, package, voltage/range/accuracy grade, lifecycle, and mating or external components. An alternate is real only after its datasheet, land pattern, electrical behavior, firmware assumptions, and assembly process have all been compared—not because a distributor search places it in the same parametric row.