PJRC Teensy 4.1 carrier PCB: design, layout, and gate checks

A dependable carrier for the PJRC Teensy 4.1 starts by treating it as a specific through-hole module, not as an interchangeable member of the Teensy 4 family. This version is built around NXP i.MX RT1062, uses Arm Cortex-M7, and occupies 61 × 17.8 mm. Its physical implementation is 48 primary 2.54 mm pins plus underside memory pads. Those details determine the land pattern, carrier outline, programming access, antenna or connector clearance, and which signals are genuinely available after the module maker has used its own pins.

Teensy 4.1 extends the 4.0 with 8 MB flash, microSD, USB host, Ethernet pads, more GPIO, and optional bottom PSRAM/flash.

Typical reasons to choose it include Ethernet and data acquisition and large audio, display, and robotics controllers. The useful comparison is therefore not merely processor speed: it is whether the exact memory, radio, connector, power path, exposed I/O, and mechanical envelope match the product that will be built. The row below is the integration baseline that should agree with the schematic, footprint, BOM, assembly drawing, and firmware target.

The carrier power tree must satisfy 5 V VIN/USB with onboard 3.3 V regulation while every external signal respects 3.3 V GPIO; Teensy 4.x pins are not 5 V tolerant. These are separate checks. A board can accept USB or VIN at one connector while its GPIO remains strictly 3.3 V, and an onboard regulator can be safe at idle yet lose regulation during a radio, display, motor, or memory-current burst. Document which source owns each rail, what happens when USB and carrier power are both present, and where bulk and high-frequency decoupling close the current loop.

Model the longer board, microSD insertion, USB host cable, Ethernet magjack route, and optional underside memory height; keep fast interfaces short and grounded.

• Use PJRC's exact 0.1-inch header, underside pad, USB host, and Ethernet pad drawings. Reserve clearance for the USB connector and any bottom-side pads the carrier contacts through pogo pins or surface-mount headers.
• The i.MX RT1062 has fast edges: keep ground returns continuous, decouple carrier loads locally, route high-speed USB and Ethernet deliberately, and avoid long unterminated traces on fast clocks and buses.

Route from a verified pin table rather than a reseller graphic. In particular, treat USB host, 100 Mbit Ethernet RMII pads, microSD, memory expansion, CAN, audio and many GPIOas design constraints that must survive schematic capture, footprint numbering, layout, production programming, and enclosure assembly. Mark orientation on copper or silkscreen, retain recovery/debug access, and make every antenna, cable, card, switch, or connector operable after the carrier is fully populated—not only while it is open on a bench.

A generic DRC run cannot know that a technically connected pin is the wrong boot strap, that a development-board header was mirrored, or that copper under an antenna will ruin range. The useful release check combines KiCad connectivity and fabrication rules with the product-specific conditions below. Each item should be supported by the selected module datasheet, hardware guide, board schematic, or mechanical drawing—not by a footprint name alone.

1. Check header drills, underside pads, board outline, USB overhang, orientation, and the extra Ethernet, SD, or memory features of the selected Teensy.
2. Check every external signal for the 3.3 V-only limit, power-source backfeed, ground continuity, and access to Program and On/Off controls.
3. Check high-speed USB, Ethernet, CAN, audio, and clock routing for correct pairs, termination, reference planes, and connector pinouts.
4. For PJRC Teensy 4.1, check Ethernet differential and magnetics path, USB host power, microSD reservations, optional memory footprints, 3.3 V limits, and Program access.

After those checks, refill every copper zone, run ERC and DRC from the same revision used to generate fabrication data, and inspect the actual Gerbers, drill file, BOM, and placement output. Confirm that the module ordering code in the BOM matches the memory and radio assumptions in firmware. A carrier is not release-ready when its prototype happens to boot; it is ready when the exact build configuration can be reproduced and inspected.

These failures recur because family names conceal physical and electrical differences. For this particular integration, watch for the following concrete mistakes:

• Routing raw Ethernet RMII pads directly to an RJ45 without the required PHY/magnetics arrangement confuses digital interface and line side.
• Applying 5 V to a Teensy 4.x GPIO based on experience with older Teensy models that had different tolerance.
• Ignoring bottom-side pads or SD-card clearance and discovering the assembled module cannot seat flat on the carrier.

Sourcing note. Use genuine Teensy 4.1 and specify whether optional PSRAM/flash is factory or carrier assembled; 4.0 is not a memory/mechanical substitute. Record the complete manufacturer code, approved alternates, module or board revision, antenna and cable when applicable, memory population, and the firmware build that was tested. If a substitute changes any of those facts, reopen the footprint, power, pinout, radio, and production-programming review instead of treating it as a purchasing-only change.