KiCad net_conflict DRC: what it means and how to fix it

drc:net_conflict is a real KiCad 9 rule identifier from the PCB Design Rules Checker. Schematic-parity checking found a footprint pad whose PCB net differs from the net expected for that symbol pin. The identifier is the stable part to use in reports, automation, and severity policy; the human-readable violation sentence can vary with the affected items and KiCad version.

This may be stale annotation/library mapping or a real electrical substitution; either way a human must reconcile the intended connectivity.

Start from the marker’s exact items and coordinates. Cross-probe them in PCB Editor → Inspect → Design Rules Checker, then inspect the surrounding net, footprint, symbol, rule scope, hierarchy, or layer state. Do not begin by changing the global rule or adding an exclusion: that can hide the symptom while leaving the wrong connectivity, fabrication geometry, library data, or schematic intent in place.

MakeIRL routes the finding to parity:net_conflict and reports recognized S2.

MakeIRL does not trust the severity label saved in a customer’s .kicad_pro. KiCad can be configured to ignore a rule entirely, so the gate authors a server-owned KiCad 9 reporting policy that forces the real catalog to be emitted and then applies its own rule-ID taxonomy. A project exclusion is recorded as evidence but never lowers the classification. Unknown identifiers also remain visible as S2 rather than disappearing or becoming an unjustified blocker.

S1 is reserved for evidence that a board is actually broken or assembly identity is impossible. S2 means a human engineering decision is required and can be acknowledged; it includes fab margins, many schematic conventions, parity drift, and rules whose intent depends on the product. S3 is advisory library, drafting, text, or silkscreen hygiene. This distinction explains why KiCad’s own “error” or “warning” word is evidence, not the release verdict.

1. 01

   Inspect the symbol pin number, footprint pad number, and net names, repair the library mapping or schematic, then use Update PCB from Schematic deliberately.

2. 02

   Open PCB Editor → Inspect → Design Rules Checker, select the marker, and cross-probe every reported item before changing a rule or adding an exclusion. Fix the design or library source so the correction survives the next schematic/PCB update.

3. 03

   Re-run parity DRC and cross-probe the affected pin/pad, confirming the resulting netlist and routed copper match the intended circuit.

If the marker came from a library defect, repair the controlled symbol or footprint first and update the schematic/board copy deliberately. If it came from a net class or custom rule, confirm the electrical, timing, safety, or fabrication requirement before changing the number. A narrow, documented rule is safer than weakening the global project to make one marker disappear. For parity findings, compare the exact MPN, symbol pin numbers, footprint pads, BOM, and placement output before accepting either side as authoritative.

Re-run parity DRC and cross-probe the affected pin/pad, confirming the resulting netlist and routed copper match the intended circuit.

Save the corrected source files, refill zones when the board contains pours, and rerun the appropriate checker from a clean state. For PCB changes, inspect Gerber, drill, solder-mask, paste, outline, and placement outputs—not only the interactive canvas. For schematic changes, regenerate the netlist/BOM and run Update PCB from Schematic so stale board state cannot survive. Cross-probe the original coordinates and confirm the intended circuit or manufacturing constraint, not merely a zero marker count.

Finally, keep the original finding, the design change, and any remaining engineering acknowledgment in the release record. That gives reviewers a traceable reason why net_conflict is resolved, accepted as a deliberate S2 decision, or retained as an S3 advisory. Silencing the rule in project settings is never the fix because it changes reporting, not the board.