Controlled-Impedance PCB Manufacturing: Stackup and DFM

This is a board attribute manufacturing profile for controlled-impedance PCB. The board profile below is a process-specific baseline that still needs order-specific confirmation, not a guaranteed price or capability.

Capabilities, prices, lead times, approved materials, assembly stock, shipping, and taxes change. Requote the exact revision and retain the supplier's order-specific confirmation before release.

• Name each single-ended/differential target, tolerance, frequency/edge context, reference layer, coupling intent, connector transition, and acceptable coupon/test plan.
• Choose the attribute because a measured electrical, thermal, mechanical, assembly, or lifecycle requirement needs it; document the requirement and the simpler alternative considered.

Route from the fabricator's field-solved geometry, keep references continuous, add return vias at layer changes, and avoid unmodeled neckdowns and stubs.

• Obtain the actual stackup, material, tolerance, coupon, panel, and process notes before routing; the same marketing label can describe materially different constructions.

• Connector launch and component-pad discontinuities remain design work; a fab impedance coupon does not validate the assembled channel.
• Check how the fabrication choice changes stencil, reflow, handling, depanelization, warpage, inspection, repair, and component compatibility.

Validation plan:

• Review TDR coupon evidence, then test the complete link at speed or with suitable SI measurements including connectors, vias, and cables.
• Measure the property that justified the attribute—impedance, temperature rise, bend life, solderability, flatness, or interconnect reliability—on representative built boards.

Cost drivers:

• Controlled material, tighter trace tolerance, engineering, coupons/TDR, stackup, panel nesting, and possible impedance class count drive cost.
• Special materials and process steps can add tooling, minimum quantity, engineering review, lower panel yield, and longer queues even when raw board area is unchanged.

• Writing '90 Ω differential' in a note without defining layer, reference, stackup, trace, spacing, and tolerance is not an impedance design.
• Paying for an attribute without encoding its constraints in the design produces a more expensive board with no guaranteed performance benefit.

Ask the fabricator directly:

• What field-solved finished width/spacing and dielectric values meet each target after etch and plating?
• Where is the coupon placed, how is it constructed relative to product traces, and what TDR report is delivered?

1. S1Schematic/PCB parity and unresolved connectivity. Run ERC, DRC with schematic parity, and netlist comparison for the controlled-impedance PCB release; explain every exclusion rather than suppressing it globally.
2. S2Quoted fabrication-profile compliance. Compare saved copper, holes, mask, outline, and field-solved trace geometry, controlled material/pressing, impedance coupon, and tdr report constraints with the exact quoted stackup and option set.
3. S1BOM, placement, polarity, and output identity. Require exact MPNs, matched BOM/CPL reference sets, reviewed rotations, one clean outline, and fabrication outputs regenerated from the approved controlled-impedance PCB source revision.