Texas Instruments TPS61023DRLR: PCB footprint and gate checks

The Texas Instruments TPS61023DRLR is a 3.7 A switch synchronous boost converter from Texas Instruments. Its package or board interface is 6-pin SOT-5X3 (DRL), and its relevant electrical envelope is 0.5–5.5 V input, adjustable output up to 5.5 V, high peak switch current. It communicates or connects through synchronous boost with enable. Those fields belong together: substituting a familiar family name while changing package, voltage, sensing port, mount style, current class, or interface behavior can leave a PCB that passes ordinary net checks and still cannot be assembled or function safely.

TPS61023 starts from very low input and uses a high-current synchronous switch for compact battery-to-5 V conversion.

Common uses include single-cell to 5 V and high-burst portable power rails. Start with the manufacturer drawing and recommended application, then record the exact ordering suffix alongside the KiCad symbol and footprint. This makes the library evidence reviewable when the part is re-sourced months later.

• Copy the recommended power-stage layout and exposed-pad treatment. The input capacitor, switch, inductor, diode where external, and output capacitor form high-di/dt loops that must stay tight.
• Keep SW copper small and feedback remote from it. Provide enough copper and vias for input current, which can be much higher than output current at low input voltage.

Keep VIN, inductor, SW and output loops extremely short, use an inductor rated for peak switch current, and provide broad battery-side copper.

• Calculate inductor peak current, switch limit, diode stress, duty cycle, startup load, output-divider tolerance, and capacitor ripple for the minimum input voltage and maximum load.
• Add input undervoltage behavior and load disconnect where the product requires true off; many boost converters leave a DC path from input to output even when disabled.

Put the support components where their current, thermal, optical, RF, or measurement loops are actually short—not merely where ratsnest lines look tidy. Confirm pin one from the package view used in the datasheet, distinguish top view from mating face or bottom view, and check mask, paste, drill, courtyard, enclosure, and rework access independently. A correct copper pad pattern can still be a bad production footprint when the sensing opening, connector latch, exposed pad, thermal path, or cable volume is wrong.

MakeIRL’s release gate should not stop at “the symbol has the right number of pins.” For this part, a useful gate review combines ERC/DRC with the following package- and function-specific evidence:

1. Check power-stage pinout, hot loops, inductor saturation, diode and capacitor voltage, feedback divider, compensation, enable, and switch current at minimum input.
2. Check input trace/current capacity, output overvoltage risk, shutdown leakage or pass-through path, thermal copper, and separation from antennas and sensors.
3. Check exact suffix, frequency, and package against the design equations and source a real IC rather than an untraceable boost-module listing.
4. For Texas Instruments TPS61023DRLR, check DRL footprint, startup/input range, output divider and 5.5 V max, 3.7 A switch current, inductor saturation, EN, caps, current traces, and heat.

Then run ERC and DRC, refill zones, and inspect the fabrication and assembly outputs. Cross-probe the exact pads named by any finding, compare the BOM MPN with the footprint and electrical limits above, and verify that a real cable, enclosure, antenna, sensor stimulus, load, or thermal path can be tested on the assembled unit. An exclusion is evidence that someone dismissed a marker; it is not evidence that the underlying condition was resolved.

The most expensive errors are usually plausible: a footprint from a sibling package, a breakout-board voltage copied to the bare IC, a headline current used without thermal analysis, or a connector family selected by pitch alone. For Texas Instruments TPS61023DRLR, review these failure modes explicitly:

• A coin cell may meet the IC voltage range but cannot supply the pulse current needed for a high-power 5 V output.
• Sizing components from output current while ignoring the much larger battery-side current demanded by conversion losses and low input voltage.
• Assuming enable disconnects the load even though the inductor/diode path continues to feed the output.

Sourcing note. Use TPS61023DRLR and validate the source impedance/battery protection; do not infer system output current from the switch rating. The approved vendor list should preserve manufacturer, full suffix, package, voltage/range/accuracy grade, lifecycle, and mating or external components. An alternate is real only after its datasheet, land pattern, electrical behavior, firmware assumptions, and assembly process have all been compared—not because a distributor search places it in the same parametric row.