RAK4631 WisBlock Core integration: PCB layout and release checks

A dependable carrier for the RAK4631 WisBlock Core starts by treating it as a specific development board, not as an interchangeable member of the LoRa development board family. This version is built around Nordic nRF52840 plus Semtech SX1262, uses MCU plus Semtech LoRa transceiver, and occupies 20 × 30 mm. Its physical implementation is 20 × 30 mm mezzanine board with two high-density WisBlock connectors. Those details determine the land pattern, carrier outline, programming access, antenna or connector clearance, and which signals are genuinely available after the module maker has used its own pins.

RAK4631 combines nRF52840 and SX1262 on a WisBlock Core board with high-density connectors and separate LoRa and BLE antenna connections.

Typical reasons to choose it include BLE-provisioned LoRaWAN nodes and modular low-power telemetry. The useful comparison is therefore not merely processor speed: it is whether the exact memory, radio, connector, power path, exposed I/O, and mechanical envelope match the product that will be built. The row below is the integration baseline that should agree with the schematic, footprint, BOM, assembly drawing, and firmware target.

The carrier power tree must satisfy 3.3 V from WisBlock base or qualified custom carrier while every external signal respects 3.3 V GPIO; USB or VIN may accept 5 V. These are separate checks. A board can accept USB or VIN at one connector while its GPIO remains strictly 3.3 V, and an onboard regulator can be safe at idle yet lose regulation during a radio, display, motor, or memory-current burst. Document which source owns each rail, what happens when USB and carrier power are both present, and where bulk and high-frequency decoupling close the current loop.

Use RAK's exact board-to-board connector footprints and stack height, leave both IPEX connectors serviceable, and keep the carrier and enclosure clear of antenna cables.

• Use the exact board revision: Heltec and RAK boards change radio, display, USB, pinout, and antenna connector between generations. Keep the antenna connector and antenna volume clear of the carrier and enclosure.
• Check USB, battery, and carrier power interactions and budget for transmit bursts plus any OLED. Preserve reset, boot, SWD/JTAG where offered, and the antenna connection for test and certification work.

Route from a verified pin table rather than a reseller graphic. In particular, treat two 40-pin mezzanine connectors carry power, RF-control, USB, SWD and buses; IPEX antenna connectors onboardas design constraints that must survive schematic capture, footprint numbering, layout, production programming, and enclosure assembly. Mark orientation on copper or silkscreen, retain recovery/debug access, and make every antenna, cable, card, switch, or connector operable after the carrier is fully populated—not only while it is open on a bench.

A generic DRC run cannot know that a technically connected pin is the wrong boot strap, that a development-board header was mirrored, or that copper under an antenna will ruin range. The useful release check combines KiCad connectivity and fabrication rules with the product-specific conditions below. Each item should be supported by the selected module datasheet, hardware guide, board schematic, or mechanical drawing—not by a footprint name alone.

1. Check header geometry, board outline, display and USB overhang, antenna connector position, and exact radio-frequency variant.
2. Check power-source isolation, battery polarity and charger behavior, 3.3 V-only GPIO, and all radio-reserved or display-reserved pins.
3. Check antenna clearance and connector access and verify the BOM names the intended regional band and antenna type.
4. For RAK4631 WisBlock Core, check regional RAK4631 SKU, both mezzanine connector maps and heights, LoRa/BLE antenna cables, 3.3 V peak current, SWD, and USB.

After those checks, refill every copper zone, run ERC and DRC from the same revision used to generate fabrication data, and inspect the actual Gerbers, drill file, BOM, and placement output. Confirm that the module ordering code in the BOM matches the memory and radio assumptions in firmware. A carrier is not release-ready when its prototype happens to boot; it is ready when the exact build configuration can be reproduced and inspected.

These failures recur because family names conceal physical and electrical differences. For this particular integration, watch for the following concrete mistakes:

• Using the wrong connector mating height can bow the module or prevent full engagement while ordinary 2D courtyard checks still pass.
• Using a footprint or pinout for an earlier board revision whose ESP chip, LoRa radio, and USB connector were changed.
• Powering the board from USB and a carrier battery circuit simultaneously without understanding the onboard charger and ideal-diode path.

Sourcing note. Control regional module, two mating connectors, stack height, antenna pigtails, and RUI firmware as one qualified assembly. Record the complete manufacturer code, approved alternates, module or board revision, antenna and cable when applicable, memory population, and the firmware build that was tested. If a substitute changes any of those facts, reopen the footprint, power, pinout, radio, and production-programming review instead of treating it as a purchasing-only change.