simulation_model_issue ERC in KiCad: cause, severity, and fix

erc:simulation_model_issue is a real KiCad 9 rule identifier from the Schematic Electrical Rules Checker. A symbol's SPICE/simulation model, pin mapping, file, or parameters are missing or invalid. The identifier is the stable part to use in reports, automation, and severity policy; the human-readable violation sentence can vary with the affected items and KiCad version.

Simulation may fail or misrepresent behavior, but fabrication data and physical connectivity can still be correct.

Start from the marker’s exact items and coordinates. Cross-probe them in Schematic Editor → Inspect → Electrical Rules Checker, then inspect the surrounding net, footprint, symbol, rule scope, hierarchy, or layer state. Do not begin by changing the global rule or adding an exclusion: that can hide the symptom while leaving the wrong connectivity, fabrication geometry, library data, or schematic intent in place.

The current gate explicitly maps this to S2 review even though it is not manufacturing-fatal.

MakeIRL does not trust the severity label saved in a customer’s .kicad_pro. KiCad can be configured to ignore a rule entirely, so the gate authors a server-owned KiCad 9 reporting policy that forces the real catalog to be emitted and then applies its own rule-ID taxonomy. A project exclusion is recorded as evidence but never lowers the classification. Unknown identifiers also remain visible as S2 rather than disappearing or becoming an unjustified blocker.

S1 is reserved for evidence that a board is actually broken or assembly identity is impossible. S2 means a human engineering decision is required and can be acknowledged; it includes fab margins, many schematic conventions, parity drift, and rules whose intent depends on the product. S3 is advisory library, drafting, text, or silkscreen hygiene. This distinction explains why KiCad’s own “error” or “warning” word is evidence, not the release verdict.

1. 01

   Open Symbol Properties → Simulation Model, fix the model file, pin mapping, primitive, and parameters, or remove an unused broken model deliberately.

2. 02

   Open Schematic Editor → Inspect → Electrical Rules Checker, select the marker, and cross-probe every reported item before changing a rule or adding an exclusion. Fix the design or library source so the correction survives the next schematic/PCB update.

3. 03

   Run the simulator/model check and ERC; compare model pin mapping with the symbol and datasheet.

If the marker came from a library defect, repair the controlled symbol or footprint first and update the schematic/board copy deliberately. If it came from a net class or custom rule, confirm the electrical, timing, safety, or fabrication requirement before changing the number. A narrow, documented rule is safer than weakening the global project to make one marker disappear. For parity findings, compare the exact MPN, symbol pin numbers, footprint pads, BOM, and placement output before accepting either side as authoritative.

Run the simulator/model check and ERC; compare model pin mapping with the symbol and datasheet.

Save the corrected source files, refill zones when the board contains pours, and rerun the appropriate checker from a clean state. For PCB changes, inspect Gerber, drill, solder-mask, paste, outline, and placement outputs—not only the interactive canvas. For schematic changes, regenerate the netlist/BOM and run Update PCB from Schematic so stale board state cannot survive. Cross-probe the original coordinates and confirm the intended circuit or manufacturing constraint, not merely a zero marker count.

Finally, keep the original finding, the design change, and any remaining engineering acknowledgment in the release record. That gives reviewers a traceable reason why simulation_model_issue is resolved, accepted as a deliberate S2 decision, or retained as an S3 advisory. Silencing the rule in project settings is never the fix because it changes reporting, not the board.