JST B4B-PH-K-S PCB footprint, checks, and sourcing guide

The JST B4B-PH-K-S is a 4-circuit top-entry through-hole connector from JST. Its package or board interface is 2.00 mm-pitch JST PH, vertical entry, and its relevant electrical envelope is 100 V and 2 A class series rating. It communicates or connects through four-wire power/signal harness. Those fields belong together: substituting a familiar family name while changing package, voltage, sensing port, mount style, current class, or interface behavior can leave a PCB that passes ordinary net checks and still cannot be assembled or function safely.

B4B-PH-K-S is a vertical four-position PH header with larger pitch and current capability than JST SH/Qwiic connectors.

Common uses include I²C harnesses outside Qwiic and small motor and encoder cables. Start with the manufacturer drawing and recommended application, then record the exact ordering suffix alongside the KiCad symbol and footprint. This makes the library evidence reviewable when the part is re-sourced months later.

• Use the exact series drawing, not pitch alone. Entry direction, latch side, boss holes, mounting tabs, and the datum used to number circuits all affect whether the cable mates and whether pin 1 is mirrored.
• Keep the mating and wire-bend envelope out of the courtyard and enclosure. Through-hole versions need finished-hole and annular-ring checks; surface-mount versions need copper balance and anchor-tab paste guidance.

Define the pinout explicitly rather than borrowing Qwiic: JST PH has no universal I²C order, and 5 V may be appropriate only if every device supports it.

• Label pin 1 and functional signals on both schematic and silkscreen. Put ground adjacent to clocks or power where the ecosystem pinout permits, and add pull-ups, ESD, reverse-polarity protection, or hot-plug protection according to what leaves the enclosure.
• Choose the housing, crimp contact, wire gauge, and cable assembly as a system. A board header MPN alone does not guarantee that procurement can buy a compatible, correctly keyed cable.

Put the support components where their current, thermal, optical, RF, or measurement loops are actually short—not merely where ratsnest lines look tidy. Confirm pin one from the package view used in the datasheet, distinguish top view from mating face or bottom view, and check mask, paste, drill, courtyard, enclosure, and rework access independently. A correct copper pad pattern can still be a bad production footprint when the sensing opening, connector latch, exposed pad, thermal path, or cable volume is wrong.

MakeIRL’s release gate should not stop at “the symbol has the right number of pins.” For this part, a useful gate review combines ERC/DRC with the following package- and function-specific evidence:

1. Check series, pitch, circuit count, entry direction, latch orientation, pin-one datum, boss holes, anchors, finished drills, and edge clearance against the exact drawing.
2. Check the ecosystem pinout and voltage, I²C pull-up ownership where applicable, connector polarity, external ESD exposure, and current per contact.
3. Check that the mating housing and crimp/contact MPNs exist in the BOM or sourcing notes and that the cable can be inserted after enclosure assembly.
4. For JST B4B-PH-K-S, check four vertical drills, pin one, latch clearance, custom cable pinout, voltage/current, I²C pull-ups if used, and ESD.

Then run ERC and DRC, refill zones, and inspect the fabrication and assembly outputs. Cross-probe the exact pads named by any finding, compare the BOM MPN with the footprint and electrical limits above, and verify that a real cable, enclosure, antenna, sensor stimulus, load, or thermal path can be tested on the assembled unit. An exclusion is evidence that someone dismissed a marker; it is not evidence that the underlying condition was resolved.

The most expensive errors are usually plausible: a footprint from a sibling package, a breakout-board voltage copied to the bare IC, a headline current used without thermal analysis, or a connector family selected by pitch alone. For JST B4B-PH-K-S, review these failure modes explicitly:

• Calling any four-pin JST connector Qwiic can invite a 1 mm SH cable or standardized pinout that this 2 mm PH part does not use.
• Mirroring pin numbers because the drawing shows the mating face while the PCB library was created from a top view.
• Selecting a connector solely by pitch and discovering the intended cable uses a different latch, polarization, or contact family.

Sourcing note. Pair the B4B header with PHR-4 housing and correct contacts or a controlled cable assembly. The approved vendor list should preserve manufacturer, full suffix, package, voltage/range/accuracy grade, lifecycle, and mating or external components. An alternate is real only after its datasheet, land pattern, electrical behavior, firmware assumptions, and assembly process have all been compared—not because a distributor search places it in the same parametric row.