Adafruit Feather RP2350 carrier PCB: layout and gate checks

A dependable carrier for the Adafruit Feather RP2350 starts by treating it as a specific through-hole module, not as an interchangeable member of the RP2040 / RP2350 family. This version is built around RP2350A, uses dual-core Arm Cortex-M0+ or dual-core Cortex-M33 / Hazard3 RISC-V, and occupies 50.8 × 22.8 mm. Its physical implementation is Feather two-row header pattern. Those details determine the land pattern, carrier outline, programming access, antenna or connector clearance, and which signals are genuinely available after the module maker has used its own pins.

Feather RP2350 combines RP2350 with 8 MB flash and 8 MB PSRAM, LiPo power, and STEMMA QT for larger buffers than the RP2040 Feather.

Typical reasons to choose it include memory-heavy battery controllers and FeatherWing RP2350 applications. The useful comparison is therefore not merely processor speed: it is whether the exact memory, radio, connector, power path, exposed I/O, and mechanical envelope match the product that will be built. The row below is the integration baseline that should agree with the schematic, footprint, BOM, assembly drawing, and firmware target.

The carrier power tree must satisfy USB-C or LiPo with charging and onboard 3.3 V regulation while every external signal respects 3.3 V I/O; ADC and digital pins must remain within the board's limits. These are separate checks. A board can accept USB or VIN at one connector while its GPIO remains strictly 3.3 V, and an onboard regulator can be safe at idle yet lose regulation during a radio, display, motor, or memory-current burst. Document which source owns each rail, what happens when USB and carrier power are both present, and where bulk and high-frequency decoupling close the current loop.

Leave USB-C, battery, and Qwiic access, keep analog signals clear of charger currents, and preserve debug and boot access for RP2350 recovery.

• Use the module's castellated or 2.54 mm header drawing exactly and reserve USB, debug, and underside test-pad access as required. RP boards integrate flash and clocks that a bare RP2040 or RP2350 design would need externally.
• Understand the board's VSYS, VBUS, 3V3, and 3V3_EN relationships before adding carrier power. Add source isolation when USB and the carrier may be live together and keep noisy loads off the ADC reference path.

Route from a verified pin table rather than a reseller graphic. In particular, treat Feather I/O plus PSRAM, STEMMA QT, NeoPixel, battery monitor and RP2350 debugas design constraints that must survive schematic capture, footprint numbering, layout, production programming, and enclosure assembly. Mark orientation on copper or silkscreen, retain recovery/debug access, and make every antenna, cable, card, switch, or connector operable after the carrier is fully populated—not only while it is open on a bench.

A generic DRC run cannot know that a technically connected pin is the wrong boot strap, that a development-board header was mirrored, or that copper under an antenna will ruin range. The useful release check combines KiCad connectivity and fabrication rules with the product-specific conditions below. Each item should be supported by the selected module datasheet, hardware guide, board schematic, or mechanical drawing—not by a footprint name alone.

1. Check row spacing, castellations or header drills, pin numbering, underside keepouts, and USB connector clearance against the exact board revision.
2. Check VBUS-versus-VSYS power direction, 3.3 V logic limits, ADC reference routing, and whether the carrier can unintentionally disable the onboard regulator.
3. Check SWD or debug access, boot-select access, complete ground connections, and continuity for every header signal used by the carrier.
4. For Adafruit Feather RP2350, verify PSRAM configuration, board-reserved signals, RP2350 firmware target, Feather header map, and 3.3 V limits.

After those checks, refill every copper zone, run ERC and DRC from the same revision used to generate fabrication data, and inspect the actual Gerbers, drill file, BOM, and placement output. Confirm that the module ordering code in the BOM matches the memory and radio assumptions in firmware. A carrier is not release-ready when its prototype happens to boot; it is ready when the exact build configuration can be reproduced and inspected.

These failures recur because family names conceal physical and electrical differences. For this particular integration, watch for the following concrete mistakes:

• Using an RP2040 Feather firmware or assuming no external PSRAM can misconfigure memory and low-level peripherals.
• Back-powering USB through VBUS or tying a carrier's 3.3 V regulator directly against the module's onboard regulator.
• Mirroring the Pico pinout when placing bottom-entry headers, which swaps every physical pin even though the net names still look plausible.

Sourcing note. Use Adafruit's exact RP2350 Feather memory and revision code; HSTX and non-HSTX versions are not automatic alternates. Record the complete manufacturer code, approved alternates, module or board revision, antenna and cable when applicable, memory population, and the firmware build that was tested. If a substitute changes any of those facts, reopen the footprint, power, pinout, radio, and production-programming review instead of treating it as a purchasing-only change.