Adafruit Feather ESP32-C6 carrier PCB: layout and gate checks

A dependable carrier for the Adafruit Feather ESP32-C6 starts by treating it as a specific development board, not as an interchangeable member of the ESP32 RISC-V family. This version is built around ESP32-C6, uses 32-bit RISC-V, and occupies 50.8 × 22.8 mm. Its physical implementation is Feather header pattern with STEMMA QT. Those details determine the land pattern, carrier outline, programming access, antenna or connector clearance, and which signals are genuinely available after the module maker has used its own pins.

Feather ESP32-C6 combines the familiar battery carrier with Wi-Fi 6 and 802.15.4, while onboard support circuits reduce the edge-pin set available to a FeatherWing.

Typical reasons to choose it include battery Matter controllers and FeatherWing multiprotocol sensors. The useful comparison is therefore not merely processor speed: it is whether the exact memory, radio, connector, power path, exposed I/O, and mechanical envelope match the product that will be built. The row below is the integration baseline that should agree with the schematic, footprint, BOM, assembly drawing, and firmware target.

The carrier power tree must satisfy USB-C or LiPo with onboard charger and 3.3 V regulation while every external signal respects 3.3 V GPIO; external signals must stay within the 3.3 V domain. These are separate checks. A board can accept USB or VIN at one connector while its GPIO remains strictly 3.3 V, and an onboard regulator can be safe at idle yet lose regulation during a radio, display, motor, or memory-current burst. Document which source owns each rail, what happens when USB and carrier power are both present, and where bulk and high-frequency decoupling close the current loop.

Keep USB-C, LiPo, STEMMA QT, and antenna access clear; place noisy carrier power away from the radio and avoid metal directly above or below its antenna end.

• Build the carrier around the exact header and underside drawing. Leave antenna and USB overhang free, label orientation clearly, and make the board removable when it is the programming and radio subsystem.
• Plan USB and carrier power as separate possible sources, then add ORing or a documented jumper. Check whether the 5 V, VBUS, and 3V3 header pins are inputs, outputs, or directly tied on the chosen board.

Route from a verified pin table rather than a reseller graphic. In particular, treat Feather I/O plus STEMMA QT, NeoPixel, battery monitor and radio-reserved pinsas design constraints that must survive schematic capture, footprint numbering, layout, production programming, and enclosure assembly. Mark orientation on copper or silkscreen, retain recovery/debug access, and make every antenna, cable, card, switch, or connector operable after the carrier is fully populated—not only while it is open on a bench.

A generic DRC run cannot know that a technically connected pin is the wrong boot strap, that a development-board header was mirrored, or that copper under an antenna will ruin range. The useful release check combines KiCad connectivity and fabrication rules with the product-specific conditions below. Each item should be supported by the selected module datasheet, hardware guide, board schematic, or mechanical drawing—not by a footprint name alone.

1. Verify row spacing, header population, USB position, pin numbering, and board outline against the exact C-series development board.
2. Check 5 V backfeed paths, 3.3 V-only I/O, boot-strap loading, and connector access after the carrier and enclosure are assembled.
3. Keep carrier copper, ground planes, batteries, and metal hardware outside the antenna keepout and inspect any external-antenna option.
4. For Adafruit Feather ESP32-C6, verify board-reserved pins, C6 protocol support, 4 MB memory budget, charger wiring, and Feather header map.

After those checks, refill every copper zone, run ERC and DRC from the same revision used to generate fabrication data, and inspect the actual Gerbers, drill file, BOM, and placement output. Confirm that the module ordering code in the BOM matches the memory and radio assumptions in firmware. A carrier is not release-ready when its prototype happens to boot; it is ready when the exact build configuration can be reproduced and inspected.

These failures recur because family names conceal physical and electrical differences. For this particular integration, watch for the following concrete mistakes:

• Porting a Feather ESP32-S3 design can assume PSRAM or assign pins not exposed by the C6 Feather.
• Using a DevKitC footprint for a shorter DevKitM or third-party board with different header coordinates.
• Assuming pin numbers and peripheral assignments match an older ESP32 dev kit simply because the Arduino framework names look familiar.

Sourcing note. Use the exact Adafruit product and revision; Feather mechanical compatibility does not authorize another Feather as a BOM alternate. Record the complete manufacturer code, approved alternates, module or board revision, antenna and cable when applicable, memory population, and the firmware build that was tested. If a substitute changes any of those facts, reopen the footprint, power, pinout, radio, and production-programming review instead of treating it as a purchasing-only change.